Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

CAP | N/A | C | 1 (and only) |
devices/cap | Enhancements over the original model: - Parallel Multiplier - Temperature difference from circuit temperature - Preliminary technology scaling support - Model capacitance - Cj calculation based on relative dielectric constant and insulator thickness |

IND | N/A | L | 1 (and only) | devices/ind | Enhancements over the original model: - Parallel Multiplier - Temperature difference from circuit temperature - Preliminary technology scaling support - Model inductance - Inductance calculation for toroids or solenoids on the model line. |

RES | N/A | R | 1 (and only) | devices/res | Enhancements over the original model: - Parallel Multiplier - Different value for ac analysis - Temperature difference from circuit temperature - Noiseless resistor - Flicker noise - Preliminary technology scaling support |

Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

CPL | N/A | P | 1 (and only) | devices/cpl | This model comes from swec and kspice. It is not documented, if you have kspice docs, can you write a short description of its use ? - Does not implement parallel code switches - Probably a lot of memory leaks Enhancements over the original model: - Better integrated into ngspice adding CPLask, CPLmAsk and CPLunsetup functions |

LTRA | N/A | O | 1 (and only) | devices/ltra | Original spice model. - Does not implement parallel code switches |

TRA | N/A | T | 1 (and only) | devices/tra | - Parallel Multiplier - Different value for ac analysis - Temperature difference from circuit temperature - Noiseless resistor - Flicker noise - Preliminary technology scaling support |

TXL | N/A | Y | 1 (and only) | devices/txl | This model comes from kspice. It is not documented, if you have kspice docs, can you write a short description of its use ? There is some code left out from compilation: TXLaccept and TXLfindBr. Any ideas ? - Does not implement parallel code switches |

URC | N/A |
U | 1 (and only) |
devices/urc | Original spice model. - Does not implement parallel code switches |

Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

ASRC | N/A | B | 1 (and only) |
devices/asrc | The arbitrary source code has been corrected with the patch available on the Internet. There is still an issue to fix, the current of current-controlled generators. |

CCCS | N/A | L | 1 (and only) | devices/cccs | Original spice model. |

CCVS | N/A | H | 1 (and only) | devices/ccvs | Original spice model. |

ISRC | N/A | I | 1 (and only) | devices/isrc | This is the original spice device improved by Alan Gillespie with the following features: - Source ramping - Check for non-monotonic series in PWL |

VCCS | N/A |
G | 1 (and only) | devices/vccs | Original spice model. |

VCVS | N/A | E | 1 (and only) |
devices/vcvs | Original spice model. |

VSRC | N/A | V | 1 (and only) |
devices/vsrc | This is the original spice device improved by Alan Gillespie with the following features: - Source ramping - Check for non-monotonic series in PWL |

Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

CSW | N/A | W | 1 (and only) | devices/asrc | This model comes from Jon Engelbert |

SW | N/A | SL | 1 (and only) | devices/sw | tdis model comes from Jon Engelbert |

Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

DIO | N/A | D | 1 (and only) |
devices/dio | Enhancements over the original model: - Parallel Multiplier - Temperature difference from circuit temperature - Forward and reverse knee currents - Periphery (sidewall) effects - Temperature correction of some parameters |

Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

BJT | N/A | Q | 1 |
devices/bjt |
Enhancements over the original model: - Parallel Multiplier - Temperature difference from circuit temperature - Different area parameters for collector, base and emitter |

BJT2 | N/A | Q | 2 |
devices/bjt2 | This is the BJT model written by Alan Gillespie to support lateral devices. The model has been hacked by Dietmar Warning fixing some bugs and adding some features (temp. correction on resistors). Enhancements over the original model: - Temperature correction on rc,rb,re - Parallel Multiplier - Temperature difference from circuit temperature - Different area parameters for collector, base and emitter |

VBIC | N/A | Q | 4 |
devices/vbic | This is the Vertical Bipolar InterCompany model. The author of VBIC is Colin McAndrew mcandrew@ieee.org Spice3 Implementation: Dietmar Warning DAnalyse GmbH warning@danalyse.de Web Site: http://www.designers-guide.com/VBIC/index.html Notes: This is the 4 terminals model, without excess phase and thermal network. |

Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

JFET | N/A | J | 1 |
devices/jfet |
This is the original spice JFET model. Enhancements over the original model: - Alan Gillespie's modified diode model - Parallel multiplier - Instance temperature as difference for circuit temperature |

JFET2 | N/A | J | 2 |
devices/jfet2 | This is the Parker Skellern model for MESFETs. Web Site: http://www.elec.mq.edu.au/cnerf/models/psmodel/ Enhancements over the original model: - Parallel multiplier - Instance temperature as difference for circuit temperature |

Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

HFET1 | N/A | Z | 5 |
devices/hfet1 |
This is the Heterostructure Field Effect Transistor model from: K. Lee, M. Shur, T. A. Fjeldly and T. Ytterdal "Semiconductor Device Modeling in VLSI", 1993, Prentice Hall, New Jersey Enhancements over the original model: - Parallel multiplier - Instance temperature as difference for circuit temperature - Added pole-zero analysis |

HFET2 | N/A | Z | 6 | devices/hfet2 | Simplified version of hfet1 Enhancements over the original model: - Parallel multiplier - Instance temperature as difference for circuit temperature - Added pole-zero analysis |

Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

MES | N/A | Z | 1 |
devices/mes |
tdis is tde original spice3 MESFET model (Statz). Enhancements over tde original model: - Parallel multiplier - Alan Gillespie junction diodes implementation Added code from macspice3f4 HFET1&2 and MESA model Original note: Added device calls for Mesfet models and HFET models provided by Trond Ytterdal as of Nov 98 |

MESA | N/A | Z | 2,3,4 |
devices/mesa | This is a multilevel model. It contains code for mesa levels 2,3 and 4 Enhancements over the original model: - Parallel multiplier - Instance temperature as difference from circuit temperature - Added pole-zero analysis |

Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

MOS1 | N/A | M | 1 | devices/mos1 | This is the so-called Schichman-Hodges model. Enhancements over the original model: - Parallel multiplier - Temperature difference from circuit temperature |

MOS2 | N/A | M | 2 | devices/mos2 | This is the so-called Grove-Frohman model. Enhancements over the original model: - Parallel multiplier - Temperature difference from circuit temperature |

MOS3 | N/A | M | 3 | devices/mos3 | Enhancements over the original model: - Parallel multiplier - Temperature difference from circuit temperature |

MOS6 | N/A | M | 6 | devices/mos6 | Enhancements over the original model: - Parallel multiplier - Temperature difference from circuit temperature |

MOS9 | N/A | M | 9 | devices/mos9 | Enhancements over the original model: - Temperature difference from circuit temperature |

BSIM1 | N/A | M | 4 | devices/bsim1 | Enhancements over the original model: - Parallel multiplier - Noise analysis BUGS: Distortion analysis probably does not work with "parallel" devices. Equations are too intricate to deal with. Any one has ideas on the subject ? |

BSIM2 | N/A | M | 5 | devices/bsim2 | Enhancements over the original model: - Parallel multiplier - Noise analysis |

BSIM3v0 | 3.0 | M | 52 | devices/bsim3v0 | Status: TO BE TESTED AND IMPROVED |

BSIM3v0 | 3.0 | M | 51 | devices/bsim3v1a | Status: TO BE TESTED AND IMPROVED This is the BSIM3v3.0 model modified by Alan Gillespie. |

BSIM3v1 | 3.1 | M | 50 | devices/bsim3v1 | Status: TO BE TESTED |

BSIM3v1 | 3.1 | M | 49 | devices/bsim3v1s | Status: TO BE TESTED AND IMPROVED This is the BSIM3v3.1 model modified by Serban Popescu. This is level 49 model. It is an implementation that supports "HDIF" and "M" parameters. |

BSIM3 | 3.2.4 | M | 8 | devices/bsim3 | Status: TO BE TESTED This is the BSIM3v3.2.4 model from Berkeley device group. You can find some test netlists with results for this model on its web site. Web site: http://www-device.eecs.berkeley.edu/ ~bsim3 Enhancements over the original model: - Parallel Multiplier - ACM Area Calculation Method - Multirevision code (supports all 3v3.2 minor revisions) - NodesetFix |

BSIM4 | 4.4.0 | M | 14 | devices/bsim4 | Status: TO BE TESTED This is the BSIM4 device model from Berkeley Device Group. Test are available on its web site. Web site: http://www-device.eecs.berkeley.edu/ ~bsim3/bsim4.html Updated to 4.4.0 YET UNTESTED. |

HiSIM | 1.2.0 | M | 64 | devices/hisim | This is the HiSIM model available from Hiroshima University (Ultra-Small Device Engineering Laboratory) Web site: http://home.hiroshima-u.ac.jp/ usdl/HiSIM.shtml http://www.starc.or.jp/kaihatu/ pdgr/hisim/index.html Enhancements over the original model: - Parallel Multiplier - NodesetFix |

Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

BSIM3SOI_FD | 2.1 | M | 55 |
devices/bsim3soi_fd |
Status: TO BE TESTED. FD model has been integrated. There is a bsim3soifd directory under the test hierarchy. Test circuits come from the bsim3soi Web site at: http://www-device.eecs.berkeley.edu/ ~bsimsoi *) rework-14: removed #ifndef NEWCONV code. |

BSIM3SOI_DD | 2.1 | M | 56 |
devices/bsim3soi_dd |
Status: TO BE TESTED. There is a bsim3soidd directory under the test hierarchy. Test circuits come from bsim3soi Web site at: http://www-device.eecs.berkeley.edu/ ~bsimsoi *) rework-14: removed #ifndef NEWCONV code. |

BSIM3SOI_PD | 2.2.1 |
M | 57 | devices/bsim3soi_pd |
Status: TO BE TESTED. PD model has been integrated. There is a bsim3soipd directory under the test hierarchy. Test circuits come from the bsim3soi Web site at: http://www-device.eecs.berkeley.edu/ ~bsimsoi *) rework-14: removed #ifndef NEWCONV code. |

BSIMSOI | 3.0 | M | 58 | devices/bsim3soi | Status: TO BE TESTED. This is the newer version from Berkeley. Usable for partially/full depleted devices. Web site at: http://www-device.eecs.berkeley.edu/ ~bsimsoi |

SOI3 | 2.6 | M | 62 | devices/soi3 | Status: TO BE TESTED Web site at: http://www.micro.ecs.soton.ac.uk/stag/ |

Other devices not released as source code

Internal Name |
Ver |
Class |
Level |
Dir |
Comments |
---|---|---|---|---|---|

EKV | 2.6 | M | 44 | devices/ekv |
Status: TO BE TESTED Note: This model is not released in source code. You have to obtain the source code from the address below. Web site at: http://legwww.epfl.ch/ekv/ |

Simulador de Circuitos "Espice" Proyecto de Innovación docente del Dpto. de Electrónica y Tecnología de los Computadores Universidad de Granada |
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Mensaje del director. | Cuestiones legales. | Equipo de trabajo. | Próximas mejoras. |